1. Field of the Invention
This disclosure relates to semiconductor devices, and, more particularly, to a multi-chip package (MCP).
2. Description of the Related Art
A multi-chip package has semiconductor chips integrated into one package. Typically, after the chips are installed on a multi-chip package (MCP) board and packaged with it, their functions and electrical characteristics such as alternating current (AC) and direct current (DC) parameters are tested to examine whether or not they meet requirements determined during the design of the MCP.
Bare chips to be installed on the MCP board are tested, discarding defective chips. However, the chips may be damaged during an internal bonding process or a packaging process. Since the MCP test is performed in the after the chips are packaged, it is difficult to individually detect defects on each chip. Furthermore, when only one of the chips is defective, the entire MCP should be discarded. Therefore, in order to individually test the chips, an additional internal circuit is provided in each chip.
FIG. 1 illustrates a chip selection method in an MCP test. As shown in FIG. 1, when an MCP includes two semiconductor memory chips, a most significant bit (MSB) address pin A24 is commonly used to select a chip to be tested. A first chip Chip1 may be selected when a logic LOW signal is input to the MSB address pin A24, and a second chip Chip2 is selected when a logic HIGH signal is input to the MSB address pin A24.
According to this one chip selection method, only one chip is selected from several semiconductor chips for a test. Since the semiconductor chips are tested one by one, the test time is inevitably long.